TSMC Adds Microchannel Cooling Technology to R&D Roadmap

Summary

TSMC's director of advanced packaging R&D, Chen Yanming, stated that microchannel cooling technology, which sets tiny fluid channels inside the chip or package structure to bring coolant closer to the heat source, improves heat transfer efficiency. TSMC has begun adopting the technology and plans to co-develop it with packaging architectures. He also noted that a CoWoS version integrating 24 HBM stacks and exceeding 14 times the reticle size is expected by 2029. From 2024 to 2029, the number of AI computing transistors integrated in a single CoWoS package will grow over 48 times, and HBM bandwidth will increase 34 times, highlighting the need for cooling technology to upgrade in tandem.